TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 192

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(4) Wait control
Note 1:For SDRAM, the above settings are not effective. Refer to Section 3.16, SDRAM controller.
Note 2:For NAND flash memory, the above settings are not effective.
BnCSL<BnWW>/<BnWR>
<BnWW3>
<BnWR3>
(a) Fixed wait-state mode
(b)
without inserting a wait state.
inserted in a write cycle, and setting the BnCSL<BnWR3:BnWR0> bits specifies the
number of wait states to be inserted in a read cycle. The external bus cycle can be
programmed as follows;
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
The external bus cycle completes in two states at minimum (25 ns at f
Setting up the BnCSL<BnWW3:BnWW0> bits specifies the number of wait states to be
can be selected from 2 (0 wait state) through 12 (10 wait states), 14 (12 wait states), 18
(16 wait states) and 22 (20 wait states).
while the
states. The bus cycle is completed if the
edge of SDCLK in the sixth state. The bus cycle is extended as long as the
remains active after sixth state.
WAIT
The bus cycle is completed in the specified number of states. The number of states
In this mode, the
<BnWW2>
<BnWR2>
pin input mode
Other than the above
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
WAIT
signal is sampled active. The minimum bus cycle in this mode is six
<BnWW1>
<BnWR1>
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
WAIT
92CF26A-191
signal is sampled. A wait state is continued to be inserted
<BnWW0>
<BnWR0>
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2 states (0 wait state), fixed wait-state mode
3 states (1 wait state), fixed wait-state mode (Default)
4 states (2 wait states), fixed wait-state mode
5 states (3 wait states), fixed wait-state mode
6 states (4 wait states), fixed wait-state mode
7 states (5 wait states), fixed wait-state mode
8 states (6 wait states), fixed wait-state mode
9 states (7 wait states), fixed wait-state mode
10 states (8 wait states), fixed wait-state mode
11 states (9 wait states), fixed wait-state mode
12 states (10 wait states), fixed wait-state mode
14 states (12 wait states), fixed wait-state mode
18 states (16 wait states), fixed wait-state mode
22 states (20 wait states), fixed wait-state mode
6 states +
(Reserved)
WAIT
WAIT
signal is sampled High at the rising
pin input mode
Number of Wait States
TMP92CF26A
SYS
WAIT
2007-11-21
= 80 MHz)
signal