TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 396

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

STATUS [2:0]
(Bit4 to bit2)
000: READY
001: DATAIN
010: FULL
011: TX_ERR
100: RX_ERR
101: BUSY
110: STALL
111: INVALID
Receiving:
Transmitting:
Device can be received.
In endpoints 1 to 7, this register is initialized to “READY” by setting transfer type at
SET_CONFIGURATION.
In endpoint 0, this register is initialized to “READY” by detecting USB reset from the
host.
This is initialized to “READY” by terminating the status stage without error.
Basically, the same as with “Receiving”.
But in transmitting, when data for transmission is set to FIFO and answer to token
from host and transfer data to host collect and received ACK, status register does not
change, and it remains “READY”. In this case, EPx_Empty_A or EPx_Empty_B
interrupt terminates the transfer correctly.
UDC set to DATAIN and generates EPx_FULL_A or EPx_FULL_B interrupt when
data is received from the host without error.
Refer to 3.16.8 (2) Details for the STATUS register.
After transfer of data to IN token from host, UDC sets TX-ER to status register when
“ACK” is not received from host. In this case, an interrupt is not generated. The hosts
re-try IN token transfer.
UDC sets RX_ERR to status register without transmitting “ACK” to host when an
error (such as a CRC-error) is detected in data of received token. In this case, an
interrupt is not generated. The hosts re-try and IN token transfer.
This status is used only for the control transfer type and it is set when a status-stage
token is received from the host after a terminated data-stage.
When status-stage can be finished, terminates correctly and returns to READY. This
is not used in the Bulk and interrupts transfer type.
This status shows that the corresponding endpoint is in STALL status.
In this status, STALL-handshake returns, except for SETUP-token. The control
endpoint returns to READY from stall condition when SETUP-token is received.
Other endpoints return to READY when initialization command of FIFO is received.
(Note) With Automatic Set_Interface request answer, requests to interface 4 to 6 may
not become to request errors. If this is a problem, in Set_Interface request answer,
set Standard Request Mode <S_INTERFACE> to “1” and use software.
This status shows that the corresponding endpoint is in UNCONFIGURED status.
In this status, the UDC has no effect when a token is received from the host.
On reset, all endpoints are set to INVALID status. Only endpoint 0 returns to READY
on receiving USB-reset. Corresponding endpoints return to READY by according to
configuration.
result of the transfer. . These depend on transfer type.
92CF26A-395
These bits show status of UDC endpoint.
The status shows whether transfer is possible or not, and the
(For the Isochronous transfer type, refer to 3.16.9.)
TMP92CF26A
2007-11-21