TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 320

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TMP92CF26AXBG

Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet

Specifications of TMP92CF26AXBG

Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
 Details

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
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3.14 Serial Channels (SIO)
• UART mode
• I/O interface mode
(Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected.
And, SIO0 includes data modulator that supports the IrDA 1.0 infrared data communication
specification.
the master controller start slave controllers via a serial link (A multi-controller system).
control circuit, transmission buffer and control circuit.
The TMP92CF26A includes 1 serial I/O channel (SIO0). For channel either UART mode
In mode 1 and mode 2, a parity bit can be added. Mode 3 has a wakeup function for making
Figure 3.14.1 is block diagrams for channel.
SIO0 is compounded mainly prescaler, serial clock generation circuit, receiving buffer and
Mode 0 (I/O interface mode)
Mode 1 (7-bit UART mode)
Mode 2 (8-bit UART mode)
Mode 3 (9-bit UART mode)
No parity
Parity
No parity
Parity
Wakeup
Start
Start
Start
Start
Start
Start
Bit0
Figure 3.14.1 Data Formats
Transfer direction
When bit8 = 1, Address (Select code) is denoted.
When bit8 = 0, Data is denoted.
Bit0
Bit0
Bit0
Bit0
Bit0
Bit0
1
Mode 1:
Mode 2:
Mode 3:
Mode 0:
92CF26A-319
2
1
1
1
1
1
1
3
2
2
2
2
2
2
For transmitting and receiving I/O data using the
synchronizing signal SCLK for extending I/O.
7-bit data
8-bit data
9-bit data
4
3
3
3
3
3
3
5
4
4
4
4
4
4
6
5
5
5
5
5
5
7
6
6
6
6
6
6
Parity Stop
Stop
7
7
7
7
Parity Stop
Stop
Bit8
8
Stop
Stop
TMP92CF26A
2007-11-21

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