TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 331

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Note: The parity error flag is cleared every time it is read. However, if a parity error is detected w¥twice in succession
Note1: In 9-Bit and 8-Bit + Parity Modes, interrupts coincide with the ninth bit pulse.
Note2: The higher the transfer rate, the later than the middle receive interrupts and errors occur.
(13) Timing generation
and the parity error flag is read between the two parity errors, it may seem as if the flag had not been cleared.
To avoid this situation, a read of the parity error flag should be riggered by a receive interrupt.
Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be
transferred) to allow checking for a framing error.
2.
3.
a.
Receiving
Transmitting
b.
Interrupt timing
Framing error timing
Parity error timing
Overrun error timing
Interrupt timing
Transmission
Interrupt
timing
Receiving
Interrupt
timing
compared with the parity bit received via the RXD pin. If they are not equal, a
parity error is generated.
the majority of the samples are 0, a Framing error is generated.
Parity error <PERR>
Framing error <FERR>
In UART Mode
I/O interface
The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is
The stop bit for the received data is sampled three times around the center. If
Mode
Mode
SCLK Output Mode
SCLK Input Mode
SCLK Output Mode
SCLK Input Mode
(bit 8)
Center of stop bit
(bit 8)
Center of last bit
Center of last bit
Just before stop bit is
transmitted
(Note)
92CF26A-330
9-Bit
9-Bit
―
Immediately after last bit. (See Figure 3.14.13.)
Immediately after rise of last SCLK signal Rising Mode, or
immediately after fall in Falling Mode. (See Figure 3.14.14.)
Timing used to transfer received to data Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See Figure 3.14.15.)
Timing used to transfer received data to Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See Figure 3.14.16.)
Center of last bit
(parity bit)
Center of stop bit
Center of last bit
(parity bit)
Center of last bit
(parity bit)
Just before stop bit is
transmitted
8-Bit + Parity
8-Bit + Parity
(Note)
Center of stop bit
Center of stop bit
Center of stop bit
Center of stop bit
Just before stop bit is
transmitted
8-Bit, 7-Bit + Parity, 7-Bit
8-Bit, 7-Bit + Parity, 7-Bit
TMP92CF26A
2007-11-21