TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 109

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

HDMATR
(097FH)
bit Symbol
Read/Write
Reset State
Function
Note: Read-modify-write instructions can be used on this register.
Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is
(256 × 7 × (1 / f
LHSYNC [period:s] = 54.95 [μs], it is assumed that HDMA transfer occurs once during
LHSYNC [period:s].
By writing “87H” to the HDMATR register, the maximum HDMA time is set to 29.9 [μs]
Since SDRAM is auto-refreshed once or less in 5.47 [μs]:
The time LDMA, ARDMA, and HDMA all occupy the bus is defined as:
Based on the above, the CPU bus stop rate is calculated as follows:
forcefully terminated at 29.9 [μs].
Timer
operation
0: Disable
1: Enable
t
t
CPU bus stop rate = t
STOP
STOP
DMATE
7
0
(ARDMA) = 2 / f
(LDMA･ARDMA･HDMA)
SYS
DMATR6
)). Since HDMA start interval [period:s] = 83.33 [ms] is longer than
6
0
= (5.47 [μs] + 33.33 [ns]+ 29.9 [μs]) / 54.95 [μs] = 64.42 [%]
DMATR5
The value to be set in <DMATR6:0> should be obtained by
STOP
SYS
HDMATR Register
5
0
92CF26A-108
[Hz] = 33.33 [ns]
“Maximum bus occupancy time / (256/ f
(LDMA･ARDMA･HDMA) [s] / LHSYNC [period:s]
Maximum bus occupancy time setting
DMATR4
4
0
“00H” cannot be set.
R/W
DMATR3
3
0
DMATR2
2
0
SYS
DMATR1
)”.
1
0
TMP92CF26A
DMATR0
2007-11-21
0
0