TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 369

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

SCL line
Internal SCL
output
SDA line
<LRB>
<BB>
<PIN>
Note: X: Don’t care
Note: Don’t write <MST> = “0”, when <MST> = “0” condition. (Cannot be restarted)
(5) Restart
change the data transfer direction.
Master Mode.
bus. The SDA line remains High and the SCL pin is released. Since a stop condition
has not been generated on the bus, other devices assume the bus to be in busy state.
SBISR<BB> = “0” or signal level “1” of SCL pin in port mode. Check the <LRB> until it
becomes 1 to check that the SCL line on a bus is not pulled down to the low-level by
other devices. After confirming that the bus remains in a free state, generate a start
condition using the procedure described in (2).
In order to satisfy the set-up time requirements when restarting, take at least 4.7 μs of
waiting time by software from the time of restarting to confirm that the bus is free
until the time to generate the start condition.
SBICR2 ← 0 0 0 1 1 0 0 0
if SBISR<BB> ≠ 0
Then
if SBISR<LRB> ≠ 1
Then
4.7 μ s Wait
SBICR1 ← X X X 1 X X X X
SBIDBR ← X X X X X X X X
SBICR2 ← 1 1 1 1 1 0 0 0
Restart is used during data transfer between a master device and a slave device to
The following description explains how to restart when the TMP92CF26A is in
Clear SBICR2<MST, TRX, and BB> to 0 and set SBICR2<PIN> to 1 to release the
And confirm SCL pin, that SCL pin is released and become bus-free state by
9
Figure 3.15.20 Timing chart for generate restart
7 6 5 4 3 2 1 0
“0” → <MST>
“0” → <TRX>
“0” → <BB>
“1” → <PIN>
92CF26A-368
Release the bus
Check if SCL pin is released.
Check if SCL pin of other device is “L” level.
Set acknowledgement mode.
Set the slave address and direction bit.
Generate start condition.
“1” → <MST>
“1” → <TRX>
“1” → <BB>
“1” → <PIN>
4.7 μ s (Min)
Start condition
TMP92CF26A
2007-11-21