TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 495

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Note: If the data transmission and reception are not performed simultaneously, data communication should be
must be set to 1.
into standby mode for the UNIT-mode reception. Writing a 1 to the SPICT<RXE> bit after
writing a 1 to the <FDPXE> bit does not immediately initiate the receive operation. This is
because the data to be transmitted at the same time has not been prepared. Transmit and
receive operation is started only after the transmit data is written into the SPITD register
where SPICT<TXE> = 1.
simultaneous transmit and receive operation.:
Receiver
Transmitter
Transmit and Receive Operation
When performing a data transmissionand reception simultaneously, the FDPXE bit
Write a 1 to the SPICT<RXE> bit after writing a 1 to the FDPXE bit to put the receiver
The figure below shows the operations of the receiver and transmitter for the
SPCLK output
SPCLK output
SPDI input
SPDO output
performed with the FDPXE bit cleared to 0.
receiving
Figure 3.17.8 Transmit and Receive Operation
Start
92CF26A-494
transmitting
Start
Bit 0
LSB
LSB
Bit 1
Bit 1
Bit 2
Bit 2
Bit 3
Bit 3
Bit 4
Bit 4
Bit 5
Bit 5 Bit 6
Bit 6
TMP92CF26A
Bit 7
2007-11-21