TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 148

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

PJ
(004CH)
PJCR
(004EH)
PJFC
(004FH)
PJDR
(0093H)
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note: A read-modify-write operation cannot be performed for the registers PJCR and PJFC.
0: Port
1: SDCKE
PJ7D
PJ7F
PJ7
7
7
7
7
1
−
0
−
1
−
(Output latch register is
0: Port
1: NDCLE
Data from external port
PJ6C
PJ6D
0: Input, 1: Output
PJ6F
PJ6
6
6
6
6
1
−
0
−
0
−
set to “1”)
Figure 3.7.33 Register for Port J
W
−
Input/Output buffer drive register for standby mode
0: Port
1: NDALE
Port J function register
PJ5C
PJ5D
PJ5F
PJ5
Port J control register
Port J drive register
5
5
5
5
0
−
0
−
1
−
92CF26A-147
Port J register
0: Port
1:
SDLUDQM
PJ4D
PJ4F
PJ4
4
4
4
4
0
−
1
−
1
−
R/W
R/W
W
0: Port
1:
SDLLDQM
PJ3D
PJ3F
PJ3
3
3
1
−
3
3
1
−
0
−
0: Port
1:
SRWR
SDWE
PJ2D
PJ2F
PJ2
2
2
1
−
1
−
2
2
0
−
,
0: Port
1:
PJ1D
PJ1F
SRLUB
PJ1
SDCAS
1
1
−
1
1
1
−
1
0
−
,
0: Port
1:
TMP92CF26A
SRLLB
PJ0D
PJ0F
PJ0
SDRAS
0
0
1
−
0
1
−
0
0
−
2007-11-21
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