TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 297

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TMP92CF26AXBG

Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet

Specifications of TMP92CF26AXBG

Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
(Value to be compared)
Match with TA0REG
Example: To output the following PWM waves on the TA1OUT pin (at f
X: Don't care, −: No change
TA01RUN
TA01MOD
TA0REG
TA1FFCR
PM
PMFC
TA01RUN
Register buffer0
overflow is detected when the TA0REG double buffer is enabled.
2
n
To achieve a 20.48μs PWM cycle by setting φT1 to 0.16 μs (at f
20.48 μs ÷ 0.16 μs = 128
2
Therefore n should be set to 7.
Since the low level period is 16.0 μs when φT1 = 0.16 μs,
set the following value for TAREG:
TA0REG
In this mode the value of the register buffer will be shifted into TA0REG if 2
Use of the double buffer facilitates the handling of low duty ratio waves.
overflow
n
= 128
16.0 μs ÷ 0.16 μs = 100 = 64H
* Clock state
MSB
← −
← 1
← 0
← X
← −
← −
← 1
7
6
X
1
1
X
X
X
X
Figure 3.12.25 Register Buffer Operation
5
X
1
1
X
X
X
X
4
X
0
0
X
X
X
X
Up counter = Q
Clcok gear :
Prescaler of clock gear : 1/2
3
X
0
1
X
X
16.0 μs
20.48 μs
2
X
1
0
1
92CF26A-296
1
0
0
1
0
1
LSB
Q
1
1
0
0
1
0
X
X
X
1
Q
2
1/1
Stop TMRA0 and clear it to 0
Select 8-bit PWM mode (cycle: 2
input clock.
Write 64H.
Clear TA1FF to 0, enable the inversion and double buffer.
Set PM1 as the TA1OUT pin.
Start TMRA0 counting.
SYS
SYS
Shift into TA0REG(Register buffer0)
= 50 MHz).
= 50 MHz):
Up counter = Q
TA0REG (Register buffer0)
write
7
) and select φT1 as the
Q
2
TMP92CF26A
2
Q
3
2007-11-21
n

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