TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 543

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

LCDHSDLY
(028FH)
LCDCTL1
(0286H)
LHSP=0
LHSP=1
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
inserted in the LHSYNC signal.
As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be
Delay time = <HSD6:0>
The phase of the LHSYNC signal can be inverted by the setting of LCDCTL1 <LVSP>.
Signal Name
LCP0 signal
LVSYNC signal
Reference LHSYNC
(with 0 delay)
LHSYNC signal
Delay control 1
(Enable width control)
LCP0
phase
0: Rising
1: Falling
LHSYNC period
LCP0P
7
7
1
LHSYNC
phase
0: Rising
1: Falling
HSD6
LHSP
6
0
6
0
LHSYNC Delay Register
LCD Control 1 Register
R/W
(Phase control)
92CF26A-542
LVSYNC
phase
0: Rising
1: Falling
HSD5
5
0
LVSP
5
1
LHSYNC signal
LLOAD
phase
0: Rising
1: Falling
HSD4
4
0
LLDP
LHSYNC delay (bits 6-0)
4
0
HSD3
W
3
0
3
HSD2
2
0
2
LVSYNC
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
HSD1
LVSW1
1
0
1
0
TMP92CF26A
R/W
2007-11-21
HSD0
LVSW0
0
0
0
0