TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 249
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TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Note: If the error address (after converted) is in the range of 000H to 007H, it indicates that an error bit exists in
1) If the error address indicated by the NDRSCAn register is in the range of 000H to
2) If the error address indicated by the NDRSCAn register is in the range of 008H to
Reed-Solomon ECC
redundant area (ECC). In this case, no error correction is needed. If the number of error bits is not more than
4 symbols, Reed-Solomon codes calculate each error bit precisely even if it is the redundant area (ECC).
007H, this error exists in the ECC area and no correction is needed in this case.
(It is not able to correct the error in the ECC area. However, if the error exists in the
ECC area, only 4symbol (include the error in the ECC area) can correct the error to this
LSI. Please be careful.)
20DH, the actual error address is obtained by subtracting this address from 20 DH.
(If the valid data is processed as 512 byte, the actual error address is obtained by
subtracting this address from 207H when the error address in the range of 008H to
207H.)
Example 1:
Example 2:
•
•
needed.
error correction process inverts the data in bits 7 and 0 at address 18AH.
083H from 207H. Thus, the error correction process inverts the data in bits 7 and
0 at address 184H.)
NDRSCAn = 005H, NDRSCDn = 04H = 00000100B
As the error address (005H) is in the range of 000H to 007H, no correction is
(Although an error exists in bit 2, no correction is needed.)
NDRSCAn = 083H, NDRSCDn = 81H = 10000001B
The actual error address is obtained by subtracting 083H from 20DH. Thus, the
(If the valid data is 512 byte, the actual error address is obtained by subtracting
If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes),
the error correction process must be repeated several times to cover the entire
page.
performed properly, the NDFC only needs to refer to the error address and
error bit. However, it may be necessary to convert the error address, as
explained below.
The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data.
Basically no calculation is needed for error correction. If error detection is
92CF26A-248
TMP92CF26A
2007-11-21
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