TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 277
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Note: The same memory address is allocated to the timer register and the register buffer 0. When <TA0RDE> = “0”,
the same value is written to the register buffer 0 and the timer register; when <TA0RDE> = “1”, only the register
buffer 0 is written to.
(3)
Timer registers 0 (TA0REG)
value set in the timer register TA0REG or TA1REG matches the value in the
corresponding up counter, the comparator match detect signal goes active. If the
value set in the timer register is 00H, the signal goes active when the up counter
overflows.
double buffer structure is enabled or disabled. It is disabled if <TA0RDE> = “0” and
enabled if <TA0RDE> = “1”.
the timer register when a 2
PPG cycle in PPG mode. Hence the double buffer cannot be used in timer mode.
overflow in PWM mode or frequency agreement in PPG mode.)
double buffer, write data to the timer register, set <TA0RDE> to “1”, and write the
following data to the register buffer. Figure 3.12.5 shows the configuration of
TA0REG.
Timer registers (TA0REG and TA1REG)
These are 8-bit registers, which can be used to set a time interval. When the
TA0REG has a double buffer structure, making a pair with the register buffer.
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s
When the double buffer is enabled, data is transferred from the register buffer to
(When using the double buffer, method of renewing timer register is only
A reset initializes <TA0RDE> to “0”, disabling the double buffer. To use the
Register buffer 0
Internal data bus
Figure 3.12.5 Configuration of timer register (TA0REG)
Shift trigger
Write
92CF26A-276
n
TA01RUN<TA0RDE>
overflow occurs in PWM mode, or at the start of the
Selector
S
B
A
Matching detection PPG cycle
2
Write to TA0REG
n
overflow of PWM
TMP92CF26A
2007-11-21
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