TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 542

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

LCDHWB8
(0299H)
LCDHSW
(0294H)
Signal Name
LCP0
LHSYNC signal
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
specified in a range of 1 to 512 pulses of the LCP0 clock.
LCP0 clock.
The enable width of the LHSYNC signal is set using LCDHSW<HSW8:0>. It can be
The enable width is represented by the following equation:
Enable width = <HSW8:0> + 1
Thus, when LCDHSW<HSW8:0> is set to “0”, the enable width is set as one pulse of the
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
HSW7
O2W9
7
0
7
0
HSW6
O2W8
6
0
6
0
Signal width Bit8,9 Register
LHSYNC width Register
92CF26A-541
LCP0 clock = 1, 2, 3 … 512 pulses
HSW5
O1W9
5
5
0
0
High width setting
LHSYNC width (bits 7-0)
HSW4
O1W8
4
0
4
0
W
W
width (bit 8)
LGOE0
HSW3
O0W8
3
0
3
0
LLOAD width (bits 9-8)
HSW2
LDW9
2
0
2
0
HSW1
LDW8
1
0
1
0
TMP92CF26A
width (bit 8)
2007-11-21
LHSYNC
HSW0
HSW8
0
0
0
0