TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 431

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TMP92CF26AXBG

Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet

Specifications of TMP92CF26AXBG

Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
 Details

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(b) Interrupt transfer type
(b-1) Interrupt transmitting mode (Toggle mode)
(b-2) Interrupt transmission mode (Not toggle mode)
transfer.
same as for transmission bulk transfer. Interrupt transfer can be transferred without
using toggle bit. In this case, if ACK handshake from host is not received, toggle bit is
renewed, and finish is normal. The UDC clears FIFO for next transfer.
from host is not received, transaction is different.
Interrupt transfer type uses the same transaction format as transmission bulk
For transmission using toggle bit, hardware setting and answer in the UDC are the
UDC operation is same as in bulk transmission mode. Please refer to section (a).
This is basically the same as bulk transmission mode. However, if ACK handshake
When ACK handshake from host is received after transmission of data packet
UDC finishes normally by above transaction. FIFO can receive next data.
If a time out occurs without receiving ACK from host,
Execute above setting. This setting is the same except for STATUS changes.
Clear FIFO.
Clear DATASET register.
Renew toggle bit and prepare for next.
Set STATUS to READY.
Clear FIFO.
Clear DATASET register.
Renew toggle bit and prepare for next.
Set STATUS to TX_ERR.
92CF26A-430
TMP92CF26A
2007-11-21

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