TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 101
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
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Price
Company:
Part Number:
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TOSHIBA
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Part Number:
TMP92CF26AXBG
Manufacturer:
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3.6.6
Note: The HDMA start interval depends on the period of the HDMA start interrupt source. However, it is also possible
Note 1: 2-1-1-1 access. Each consecutive address can be accessed in 1 state.
Note 2: The transfer speed varies depending on the combination of source and destination.
Note 3: In the case of 0 waits
Read / Write
Read / Write
act as the bus master apart from the CPU. Therefore, care must be exercised to enable each
of these functions to operate smoothly.
transfer operation performed by the DMA controller is defined as “HDMA”, the display
RAM read operation performed by the LCD controller as “LDMA”, and the SDRAM auto
refresh operation performed by the SDRAM controller as “ARDMA”.
same time.
(1) CPU + HDMA
Considerations for Using More Than One Bus Master
CPU bus stop rate = t
HDMA start interval [s] = HDMA start interrupt period [s]
t
In the TMP92CF26A, the LCD controller, SDRAM controller, and DMA controller may
To facilitate explanation of DMA operation performed by each bus master, the DMA
The following explains various cases where two or more bus masters may operate at the
STOP
a) When the source or destination is internal RAM or internal I/O (SFR), burst access (6-1-1-1 access) is
b) When the source or destination is other than internal RAM or internal I/O, 1-word access is used.
to start HDMA by software.
the CPU and getting a bus acknowledgement. The DMA controller may be active while
the CPU is in HALT mode (IDLE2 mode only), in which case HDMA does not interfere
with the CPU operation. However, if HDMA is started while the CPU is active, the CPU
cannot execute instructions while HDMA is being performed.
stop time (defined as “t
interval, and number of channels to be used.
possible. Only consecutive addresses on the same page can be accessed in 1 state. Additional 4
states are needed at the end of each burst access.
The DMA controller performs DMA transfer (HDMA) after issuing a bus request to
Before activating the DMA controller, therefore, it is necessary to estimate the CPU
Read
Write
Read
Write
(HDMA) [s] = (Source read time + Destination write time) × Transfer count + α
Memory Type
I/O Type
Internal RAM
1 / 4
STOP
1 / 4
2 / 4
(Note 1)
I2S
−
STOP
(HDMA)[s] / HDMA start interval [s]
92CF26A-100
state/byte
state/byte
(HDMA)”) based on the transfer time, transfer start
1 word 6 / 2
1 word 3 / 2
Burst 1 / 2
Burst 1 / 2
External SDRAM
16-bit bus
NANDF
2 / 2
2 / 2
(Note 2)
(Note 2)
(Note 2)
(Note 2)
External SRAM
USB
2 / 2
2 / 2
2 / 2
2 / 2
16-bit bus
(Note 3)
(Note 3)
External SRAM
2 / 1
2 / 1
2 / 4
2 / 4
SPI
8-bit bus
TMP92CF26A
(Note 3)
(Note 3)
2007-11-21
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