XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 96

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
96
PSDONE
PSCLK
CLKFB
CLKFX
CLKIN
DO(0)
DO(1)
DO(2)
PSEN
DO(3)
Status Flags
•
•
The example in
shift overflow and CLKIN/CLKFB/CLKFX failure.
•
Clock Event 1
At T
exactly one clock period; otherwise, a single increment/decrement of phase shift is not
guaranteed. Also, the PSINCDEC value at T
determines whether it is an increment (logic High) or a decrement (logic Low).
Clock Event 2
At T
or decrement of the DCM outputs. PSDONE is High for exactly one clock period when
the phase shift is complete. The time required for a complete phase shift will vary. As
a result, PSDONE must be monitored for phase-shift status.
Clock Event 1
Prior to the beginning of this timing diagram, CLK0 (not shown) is already phase-
shifted at its maximum value. At clock event 1, PSDONE is asserted. However, since
the DCM has reached its maximum phase-shift capability no phase adjustment is
performed. Instead, the phase-shift overflow status pin DO[0] is asserted to indicate
this condition.
1
DMCCK_PSEN
DMCKO_PSDONE
2
Figure 2-23: Status Flags Example
Figure 2-23
, before clock event 1, PSEN is asserted. PSEN must be active for
, after clock event 2, PSDONE is asserted to indicate one increment
www.xilinx.com
shows the behavior of the status flags in the event of a phase-
3
257 - 260 Cycles
DMCCK_PSINCDEC
UG070 (v2.6) December 1, 2008
4
Virtex-4 FPGA User Guide
, before clock event 1,
ug070_2_22_071504
R