XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 157

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 4-14: FIFO Timing Parameters (Continued)
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Notes:
1. T
2. In the
3. In the
4. T
5. In the
T
T
T
T
T
FCO_FULL
FCO_RDERR
FCO_WRERR
FCO_RDCOUNT
FCO_WRCOUNT
T
FCKO_DO
FCKO_FLAGS
FCDCK_DI
Parameter
Virtex-4 Data
Virtex-4 Data
Virtex-4 Data
FIFO Timing Characteristics
R
includes parity output (T
includes parity inputs (T
.
Sheet, T
Sheet, T
Sheet, WRITE and READ enables are combined into T
Reset to FULL output
Reset to read error output
Reset to write error
output
Reset to read pointer
output
Reset to write pointer
output
The various timing parameters in the FIFO are described in this section. There is also
additional data on FIFO functionality. The timing diagrams describe the behavior in these
five cases.
•
•
•
•
•
FCKO_AEMPTY
FCKO_RDCOUNT
“Case 1: Writing to an Empty FIFO”
“Case 2: Writing to a Full or Almost Full FIFO”
“Case 3: Reading From a Full FIFO”
“Case 4: Reading From an Empty or Almost Empty FIFO”
“Case 5: Resetting All Flags”
Function
FCKO_DOP
FCDCK_DIP
, T
FCKO_AFULL
and T
).
).
FCKO_WRCOUNT
WRCOUNT
, T
RDCOUNT
www.xilinx.com
Control
WRERR
RDERR
FCKO_EMPTY
Signal
FULL
are combined into T
, T
FCKO_FULL
Time after reset that the FULL signal is stable at the
FULL outputs of the FIFO.
Time after reset that the Read error signal is stable at
the RDERR outputs of the FIFO.
Time after reset that the Write error signal is stable at
the WRERR outputs of the FIFO.
Time after reset that the Read pointer signal is stable
at the RDCOUNT outputs of the FIFO.
Time after reset that the Write pointer signal is stable
at the WRCOUNT outputs of the FIFO.
FCCK_EN
.
, T
FCKO_RDERR
FIFO Timing Models and Parameters
FCKO_POINTERS
Description
, T
FCKO_WRERR
.
are combined into
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