XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 41

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Regional Clock Buffer - BUFR
R
BUFIO Use Models
In
implementation is ideal in source-synchronous applications where a forwarded clock is
used to capture incoming data.
The regional clock buffer (BUFR) is another new clock buffer available in Virtex-4 devices.
BUFRs drive clock signals to a dedicated clock net within a clock region, independent from
the global clock tree. Each BUFR can drive the two regional clock nets in the region it is
located, and the two clock nets in the adjacent clock regions (up to three clock regions).
Figure
Clock Capable I/O
Clock Capable I/O
1-19, a BUFIO is used to drive the I/O logic using the clock capable I/O. This
Figure 1-19: BUFIO Driving I/O Logic In a Single Clock Region
www.xilinx.com
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
BUFIO
Regional Clocking Resources
BUFR
To Adjacent
Region
To Adjacent
Region
ug070_1_19_072204
To Fabric
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