XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 118

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
118
Read Operation
Write Operation
Operating Modes
WRITE_FIRST or Transparent Mode (Default)
The read operation uses one clock edge. The read address is registered on the read port,
and the stored data is loaded into the output latches after the RAM access time.
A write operation is a single clock-edge operation. The write address is registered on the
write port, and the data input is stored in memory.
There are three modes of a write operation. The “read during write” mode offers the
flexibility of using the data output bus during a write operation on the same port. Output
mode is set during device configuration. These choices increase the efficiency of block
RAM memory at each clock cycle.
Three different modes are used to determine data available on the output latches after a
write clock edge: WRITE_FIRST, READ_FIRST, and NO_CHANGE.
Mode selection is set by configuration. One of these three modes is set individually for
each port by an attribute. The default mode is WRITE_FIRST.
In WRITE_FIRST mode, the input data is simultaneously written into memory and stored
in the data output (transparent write), as shown in
Data Out
ENABLE
Address
Data In
CLK
WE
DISABLED
0000
Figure 4-2:
www.xilinx.com
XXXX
aa
READ
MEM(aa)
WRITE_FIRST Mode Waveforms
1111
bb
MEM(bb)=1111
WRITE
1111
Figure
2222
cc
MEM(cc)=2222
4-2.
WRITE
UG070 (v2.6) December 1, 2008
2222
Virtex-4 FPGA User Guide
dd
ug070_4_02_071204
XXXX
READ
MEM(dd)
R