XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 365

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Advanced SelectIO Logic Resources
Introduction
Input Serial-to-Parallel Logic Resources (ISERDES)
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
The Virtex-4 FPGA I/O functionality is described in
user guide.
•
•
This chapter covers additional Virtex-4 FPGA resources:
•
•
The Virtex-4 FPGA ISERDES is a dedicated serial-to-parallel converter with specific
clocking and logic features designed to facilitate the implementation of high-speed source-
synchronous applications. The ISERDES avoids the additional timing complexities
encountered when designing deserializers in the FPGA logic.
ISERDES features include:
•
•
Chapter 6
and their compliance with many industry standards.
Chapter 7
or DDR data.
Input serial-to-parallel converters (ISERDES) and output parallel-to-series converters
(OSERDES) support very fast I/O data rates, and allow the internal logic to run up to
ten times slower than the I/O.
The Bitslip submodule can re-align data to word boundaries, detected with the help of
a training pattern.
Dedicated Deserializer/Serial-to-Parallel Converter
The ISERDES deserializer enables high-speed data transfer without requiring the
FPGA fabric to match the input data frequency. This converter supports both single
data rate (SDR) and double data rate (DDR) modes. In SDR mode, the serial-to-parallel
converter creates a 2-, 3-, 4-, 5-, 6-, 7-, or 8-bit wide parallel word. In DDR mode, the
serial-to-parallel converter creates a 4-, 6-, 8-, or 10-bit-wide parallel word.
Digitally Controlled Delay Element – IDELAY
Every ISERDES block contains a programmable absolute delay element called
IDELAY. IDELAY is a 64-tap, wraparound, delay element with a fixed, guaranteed tap
resolution (see
registered input path, or both. There are three modes of operation:
a.
b. FIXED – Delay value is set to the value in the IOBDELAY _VALUE
DEFAULT – Zero-hold time delay mode (similar to the Virtex®-II and Virtex-II Pro
FPGA delay elements)
covers the electrical characteristics of input receivers and output drivers,
describes the register structures dedicated for sending and receiving SDR
Virtex-4 Data
www.xilinx.com
Sheet). It can be applied to the combinatorial input path,
Chapter 6
through
Chapter 8
Chapter 8
of this
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