XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 119

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Conflict Avoidance
R
READ_FIRST or READ-BEFORE-WRITE Mode
NO_CHANGE Mode
Asynchronous Clocking
In READ_FIRST mode, data previously stored at the write address appears on the output
latches, while the input data is being stored in memory (read before write). See
In NO_CHANGE mode, the output latches remain unchanged during a write operation.
As shown in
operation on the same port. NO_CHANGE mode is not supported in 32K x 1 RAM
configuration.
Virtex-4 FPGA block RAM is a true dual-port RAM, where both ports can access any
memory location at any time. When accessing the same memory location from both ports,
the user must, however, observe certain restrictions, specified by the clock-to-clock setup
time window. There are two fundamentally different situations: The two ports either have
a common clock (“synchronous clocking”), or the clock frequency or phase is different for
the two ports (“asynchronous clocking”).
Asynchronous clocking is the more general case, where the active edges of both clocks do
not occur simultaneously:
Data Out
Data Out
ENABLE
ENABLE
Address
Address
Data In
Data In
CLK
CLK
WE
WE
Figure
DISABLED
DISABLED
0000
0000
4-4, data output is still the last read data and is unaffected by a write
Figure 4-4: NO_CHANGE Mode Waveforms
Figure 4-3: READ_FIRST Mode Waveforms
www.xilinx.com
XXXX
XXXX
aa
aa
READ
READ
MEM(aa)
MEM(aa)
Synchronous Dual-Port and Single-Port RAMs
1111
bb
MEM(bb)=1111
1111
bb
MEM(bb)=1111
WRITE
WRITE
old MEM(bb)
2222
cc
2222
cc
MEM(cc)=2222
MEM(cc)=2222
WRITE
WRITE
old MEM(cc)
dd
dd
ug070__4_03_071204
ug070_4_04_071204
XXXX
XXXX
READ
READ
MEM(dd)
MEM(dd)
Figure
4-3.
119