XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 178

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
Built-in Block RAM Error Correction Code
178
WRADDR[8:0]
RDADDR[8:0]
STATUS[1:0]
DO[63:0]
DI[63:0]
Top-Level View of the Block RAM ECC Architecture
Two vertically adjacent block RAMs can be configured as a single 512 x 64 RAM with built
in Hamming error correction, using the extra eight bits in the 72-bit wide RAM. The
operation is transparent to the user. The eight protection bits are generated during each
write operation, and are used during each read operation to correct any single error, or to
detect (but not correct) any double error. Two status outputs indicate the three possible
read results: No error, single error corrected, double error detected. The read operation
does not correct the error in the memory array, it only presents corrected data on DO.
This error correction code (ECC) configuration option is available with almost all block
RAM pairs as long as the lower RAM is instantiated in an even numbered row. However,
the ECC configuration cannot use the one block RAM immediately above or below the
PowerPC® 405 blocks in Virtex-4 devices.
The functionality of the block RAM is changed when using the ECC mode.
•
•
•
•
•
Figure 4-34
64
64
2
The two block RAM ports still have independent address, clocks, and enable inputs,
but one port is a dedicated write port, and the other is a dedicated read port.
DO represents the read data after correction.
DO stays valid until the next active read operation.
Simultaneous reading and writing, even with asynchronous clocks, is allowed, but
requires careful clock timing if read and write addresses are identical.
The READ_FIRST or WRITE_FIRST modes of the normal block RAM operation are
not applicable to the ECC configuration.
Figure 4-34: Top-Level View of Block RAM ECC
Decode
Encode
Correct
64-bit
shows the top-level view of a Virtex-4 FPGA block RAM in ECC mode.
ECC
and
wraddr
wraddr
rdaddr
rdaddr
Data Out
Data In
www.xilinx.com
1
0
Q D
72
72
36
36
36
UG070 (v2.6) December 1, 2008
9
9
9
9
36
Virtex-4 FPGA User Guide
Block RAM
Block RAM
512 x 36
512 x 36
ug070_4_34_030708
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