XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 148

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
148
EMPTY Latency
Programmable ALMOSTFULL and ALMOSTEMPTY flags are brought out to give the user
an early warning when the FIFO is approaching its limits. Both these flag values can be set
by configuration to (almost) anywhere in the FIFO address range.
Two operating modes affect the reading of the first word after the FIFO was empty:
•
•
The rising edge of EMPTY is fast, and inherently synchronous with RDCLK. The empty
condition can only be terminated by WRCLK, asynchronous to RDCLK. The falling edge of
EMPTY must, therefore, artificially be moved onto the RDCLK time domain. Since the two
clocks have an unknown phase relationship, it takes several cascaded flip-flops to
guarantee that such a move does not cause glitches or metastable problems. The falling
edge of EMPTY is thus delayed by several RDCLK periods after the first write into the
previously empty FIFO. This delay guarantees proper operation under all circumstances,
and causes an insignificant loss of performance after the FIFO had gone empty.
Table 4-9
Table 4-9: FIFO Capacity
4k+1 entries by 4 bits
2k+1 entries by 9 bits
1k+1 entries by 18 bits
512+1 entries by 36 bits
In Standard mode, the first word written into an empty FIFO will appear at DO after
the user has activated RDEN. The user must “pull” the data out of the FIFO.
In FWFT mode, the first word written into an empty FIFO will automatically appear
at DO without the user activating RDEN. The FIFO “pushes” the data onto DO. The
next RDEN will then “pull” the subsequent data word onto DO.
Standard Mode
shows the FIFO capacity in the two modes.
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4k+2 entries by 4 bits
2k+2 entries by 9 bits
1k+2 entries by 18 bits
512+2 entries by 36 bits
FWFT Mode
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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