XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 46

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Clock Resources
46
Verilog Template
port(
end component;
--Example BUFGCTRL instantiation
U_BUFGCTRL : BUFGCTRL
Port map (
--Declaring constraints in VHDL file
attribute INIT_OUT
attribute PRESELECT_I0 : boolean;
attribute PRESELECT_I1 : boolean;
attribute LOC : string;
attribute INIT_OUT of U_BUFGCTRL: label is 0;
attribute PRESELECT_I0 of U_BUFGCTRL: label is FALSE;
attribute PRESELECT_I1 of U_BUFGCTRL: label is FALSE;
attribute LOC of U_BUFGCTRL: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
//Example BUFGCTRL module declaration
module BUFGCTRL (O, CE0, CE1, I0, I1, IGNORE0, IGNORE1, S0, S1);
);
O: out std_ulogic;
CE0: in
CE1: in
I0: in
I1
IGNORE0: in
IGNORE1: in
S0: in
S1: in
);
O => user_o,
CE0 => user_ce0,
CE1 => user_ce1,
I0 => user_i0,
I1 => user_i1,
IGNORE0 => user_ignore0,
IGNORE1 => user_ignore1,
S0 => user_s0,
S1 => user_s1
);
output O;
input CE0;
input CE1;
input I0;
input I1;
input IGNORE0;
input IGNORE1;
input S0;
input S1;
parameter INIT_OUT = 0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
PRESELECT_I0 : boolean := false;
PRESELECT_I1 : boolean := false;
std_ulogic;
std_ulogic;
std_ulogic
std_ulogic;
std_ulogic;
: in
std_ulogic;
std_ulogic;
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std_ulogic;
: integer;
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R