XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 225

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Fully Synchronous Shift Registers
Static-Length Shift Registers
R
All shift-register primitives and submodules do not use the register(s) available in the
same slice(s). To implement a fully synchronous read and write shift register, output pin Q
must be connected to a flip-flop. Both the shift register and the flip-flop share the same
clock, as shown in
This configuration provides a better timing solution and simplifies the design. Because the
flip-flop must be considered to be the last register in the shift-register chain, the static or
dynamic address should point to the desired length minus one. If needed, the cascadable
output can also be registered in a flip-flop.
The cascadable16-bit shift register implements any static length mode shift register
without the dedicated multiplexers (MUXF5, MUXF6,…).
shift register. Only the last SRLC16E primitive needs to have its address inputs tied to
0111. Alternatively, shift register length can be limited to 39 bits (address tied to 0110)
and a flip-flop can be used as the last register. (In an SRLC16E primitive, the shift register
length is the address input + 1.)
0111 4
D
Address
D
D
D
A[3:0]
CLK
SRLC16
SRLC16
SRLC16
CE
LUT
LUT
LUT
D
Q15
Q15
Q15
Q
Figure
Figure 5-32: 40-bit Static-Length Shift Register
Figure 5-31: Fully Synchronous Shift Register
(Write Enable)
Shift Registers (SRLs) Primitives and Verilog/VHDL Example
OUT
(40-bit SRL)
SRLC16E
www.xilinx.com
5-31.
Q
0110
D
Q15
D
D
D
A[3:0]
SRLC16
SRLC16
SRLC16
LUT
LUT
LUT
Q15
Q15
Q15
D
Q
Figure 5-32
FF
Q
D
FF
Synchronous
Output
UG070_5_31_031208
illustrates a 40-bit
Q
UG070_5_32_031208
OUT
(40-bit SRL)
225