XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 326

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
326
CE
Q1
Q2
C
D
D0A D1A D2A
SAME_EDGE_PIPELINED Mode
Figure 7-7: Input DDR Timing in SAME_EDGE_PIPELINED Mode
In the SAME_EDGE_PIPELINED mode a fourth register (IFF3), clocked by the rising-edge
clock, is placed on the output of the two registers.
registers and the signals involved using the SAME_EDGE_PIPELINED mode.
By adding the additional register, data is presented into the FPGA fabric on the same clock
edge. Unlike the SAME_EDGE mode, the additional registers do not cause the data pair to
be separated. However, an additional clock latency is required to remove the separated
effect of the SAME_EDGE mode.
using the SAME_EDGE_PIPELINED mode. The output pairs, Q1 and Q2 are presented to
the FPGA fabric at the same time.
CLK
CE
D
R
D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A
S
D0A
D1A
Figure 7-6: Input DDR in SAME_EDGE_PIPELINED Mode
www.xilinx.com
D2A
D3A
Figure 7-7
D
R
CE
D
R
CE
CLK
CLK
D4A
D5A
S
S
Q
Q
shows the timing diagram of the input DDR
Figure 7-6
D6A
D7A
D
R
CE
D
R
CE
CLK
CLK
UG070 (v2.6) December 1, 2008
shows the input DDR
S
S
Virtex-4 FPGA User Guide
D9A
D8A
Q
Q
ug070_7_06_072904
ug070_7_07_072904
Q1
Q2
D10A
D11A
R