XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 124

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
Block RAM Library Primitives
Block RAM Port Signals
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Clock - CLK[A|B]
Enable - EN[A|B]
RAMB16 is the block RAM library primitive. It is the basic building block for all block
RAM configurations. Other block RAM primitives and macros are based on this primitive.
Some block RAM attributes can only be configured using this primitive (e.g., pipeline
register, cascade). See
Figure 4-9
Each block RAM port operates independently of the other while accessing the same set of
18 Kbit memory cells.
Each port is fully synchronous with independent clock pins. All port input pins have setup
time referenced to the port CLK pin. The output data bus has a clock-to-out time
referenced to the CLK pin. Clock polarity is configurable (rising edge by default).
The enable pin affects the read, write, and set/reset functionality of the port. Ports with an
inactive enable pin keep the output pins in the previous state and do not write data to the
memory cells. Enable polarity is configurable (active High by default).
illustrates all the I/O ports of the block RAM primitive (RAMB16).
Figure 4-9: Block RAM Port Signals (RAMB16)
“Block RAM Attributes,” page
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CASCADEOUTA
CASCADEINA
DIA
DIPA
ADDRA
WEA
ENA
REGCEA
SSRA
DIB
DIPB
ADDRB
WEB
ENB
REGCEB
SSRB
CLKA
CLKB
CASCADEOUTB
CASCADEINB
DOPA
DOPB
DOA
DOB
127.
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UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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