XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 305

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
The total impedance of the LVTTL/LVCMOS driver added to the series termination
resistor R
undershoot. An IBIS simulation is advised for calculating the exact value needed for R
The connection scheme shown in
performance may be degraded by R
value and performance with an IBIS simulation.
When designing with the LVDCI_33 standard:
•
•
•
In addition, changing the slew rate from fast to slow and/or reducing the current drive
could significantly reduce overshoot and undershoot.
The
designers and signal integrity engineers.
External Device
LVTTL/
LVCMOS
Driver
The output drive strength and slew rates are not programmable. The output
impedance references the VRP and VRN resistors, and the output current is
determined by the output impedance.
If only LVDCI_33 inputs are used, it is not necessary to connect VRP and VRN to
external reference resistors. The implementation pad report does not record VRP and
VRN being used. External reference resistors are required only if LVDCI_33 outputs
are present in a bank.
LVDCI_33 is compatible with LVTTL and LVCMOS standards only.
Virtex-4 PCB Designer’s Guide
Figure 6-79: Connecting LVTTL or LVCMOS Using the LVDCI_33 Standard
0
must match the board trace impedance ±10 percent to minimize overshoot and
OBUFT_LVDCI_33
R
R
Z
IBUF_LVDCI
0
0
0
Virtex-4
= 50Ω (typical)
+ R
FPGA
Driver
Figure 6-80: 3.3V I/O Configuration
www.xilinx.com
Z
0
=
Figure 6-80
contains additional design information to assist PCB
0
. Therefore, it is also recommended to verify the R
IBUF_LVDCI_33
Z
0
Virtex-4 FPGA
OBUF_LVDCI_33
V
CCO
is for a bidirectional bus scenario. The signal
= 3.3V
I/O Standards Special Design Rules
R
0
VRN
VRP
External Device
V
CCO
ug070_6_78_071404
R
R
Z
REF
REF
0
Any 3.3V
I/O Device
UG070_6_77_031108
0
305
0
.