XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 145

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Block RAM Timing Characteristics
R
Clock Event 1
Clock Event 2
The timing diagram in
without the optional output register. The timing for read-first and no-change modes are
similar. For timing using the optional output register, an additional clock latency appears
at the DO pin.
At time 0, the block RAM is disabled; EN (enable) is Low.
Read Operation
During a read operation, the contents of the memory at the address on the ADDR inputs
are unchanged.
•
•
•
Write Operation
During a write operation, the content of the memory at the location specified by the
address on the ADDR inputs is replaced by the value on the DI pins and is immediately
reflected on the output latches (in WRITE-FIRST mode); EN (enable) is High.
•
•
ADDR
WEN
** SRVAL = 0101
SSR
CLK
* Write Mode = "WRITE_FIRST"
DO
EN
T
the block RAM.
At time T
block RAM, enabling the memory for the READ operation that follows.
At time T
become stable at the DO pins of the block RAM.
At time T
inputs of the block RAM.
At time T
the block RAM.
DI
RCCK_ADDR
Disabled
RCCK_EN
RCKO_DO
RCCK_ADDR
RDCK_DI
1
T RCCK_WEN
T RDCK_DI
T RCCK_ADDR
T RCCK_EN
DDDD
before clock event 1, address 00 becomes valid at the ADDR inputs of
00
T RCKO_DO
Read
before clock event 2, data CCCC becomes valid at the DI inputs of
MEM (00)
Figure 4-12: Block RAM Timing Diagram
before clock event 1, enable is asserted High at the EN input of the
Figure 4-12
after clock event 1, the contents of the memory at address 00
before clock event 2, address 0F becomes valid at the ADDR
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2
CCCC
0F
describes a single-port block RAM in write-first mode
Write
CCCC*
3
T RCCK_SSR
BBBB
7E
Read
MEM (7E)
Block RAM Timing Model
4
AAAA
8F
Reset
0101**
ug070_4_12_071204
5
0000
Disabled
20
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