XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 82

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
Connecting DCMs to Other Clock Resources in Virtex-4 Devices
Application Examples
82
IBUFG to DCM
DCM to BUFGCTRL
BUFGCTRL to DCM
DCM to and from PMCD
Standard Usage
Most DCM functions require connection to dedicated clock resources, including dedicated
clock I/O (IBUFG), clock buffers (BUFGCTRLs), and PMCD. These clock resources are
located in the center column of the Virtex-4 devices. This section provides guidelines on
connecting the DCM to dedicated clock resources.
Virtex-4 devices contain either 16 or 32 clock inputs. These clock inputs are accessible by
instantiating the IBUFG component. Each top and bottom half of a Virtex-4 device contains
eight or 16 IBUFGs. Any of the IBUFG in top or bottom half of the Virtex-4 device can drive
the clock input pins (CLKIN, CLKFB, PSCLK, or DCLK) of a DCM located in the same
top/bottom half of the device.
Any DCM clock output can drive any BUFGCTRL input in the same top/bottom half of
the device. There are no restrictions on how many DCM outputs can be used
simultaneously.
Any BUFGCTRL can drive any DCM in the Virtex-4 devices. However, only up to eight
dedicated clock routing resources exist in a particular clock region. Since the clock routing
is accessed via the BUFGCTRL outputs, this indirectly limits the BUFGCTRL to DCM
connection. If eight BUFGCTRL outputs are already accessing a clock region, and a DCM is
in that region, then no additional BUFGCTRL can be used in that region, including a
connection to the FB pin of the DCM.
Refer to the PMCD chapter:
The Virtex-4 FPGA DCM can be used in a variety of creative and useful applications. The
following examples show some of the more common applications.
The circuit in
access to RST and LOCKED pins. This example shows the simplest use case for a DCM.
Figure 2-8
shows DCM_BASE implemented with internal feedback and
www.xilinx.com
“Phase-Matched Clock Dividers
UG070 (v2.6) December 1, 2008
(PMCDs)”.
Virtex-4 FPGA User Guide
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