XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 34

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Clock Resources
34
In
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BUFGMUX_1 is rising edge sensitive and held at High prior to input switch.
illustrates the timing diagram for BUFGMUX_1. A LOC constraint is available for
BUFGMUX and BUFGMUX_1.
In
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Figure
Figure
The current clock is I0.
S is activated High.
If I0 is currently High, the multiplexer waits for I0 to deassert Low.
Once I0 is Low, the multiplexer output stays Low until I1 transitions High to Low.
When I1 transitions from High to Low, the output switches to I1.
If the setup/hold times are met, no glitches or short pulses can appear on the output.
The current clock is I0.
S is activated High.
If I0 is currently Low, the multiplexer waits for I0 to be asserted High.
Once I0 is High, the multiplexer output stays High until I1 transitions Low to High.
When I1 transitions from Low to High, the output switches to I1.
If the setup/hold times are met, no glitches or short pulses can appear on the output.
1-9:
1-10:
Figure 1-10: BUFGMUX_1 Timing Diagram
I0
I1
S
O
www.xilinx.com
T
BCCKO_O
T
BCCCK_CE
UG070_1_10_082504
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Figure 1-10
R