XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 389

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 8-7: OSERDES Port List and Definitions (Continued)
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
OCE
REV
SHIFTIN1
SHIFTIN2
SR
T1 to T4
TCE
Port Name
R
Input
Input
Input
Input
Input
Input
Input
Type
Data Path Output – OQ
3-state Control Output – TQ
High-Speed Clock Input – CLK
Divided Clock Input – CLKDIV
Parallel Data Inputs – D1 to D6
Output Data Clock Enable – OCE
Parallel 3-State Inputs – T1 to T4
The OQ port is the data output port of the OSERDES module. Data at the input port D1
appears first at OQ. This port connects the output of the data parallel-to-serial converter to
the data input of the IOB.
This port is the 3-state control output of the OSERDES module. When used, this port
connects the output of the 3-state parallel-to-serial converter to the control/3-state input of
the IOB.
This high-speed clock input drives the serial side of the parallel-to-serial converters.
This divided high-speed clock input drives the parallel side of the parallel-to-serial
converters. This clock is the divided version of the clock connected to the CLK port.
All incoming parallel data enters the OSERDES module through ports D1 to D6. These
ports are connected to the FPGA fabric, and can be configured from two to six bits (i.e., a
6:1 serialization). Bit widths greater than six (up to 10) can be supported by using a second
OSERDES in SLAVE mode (see
page 369
corresponding bit order of the ISERDES.
OCE is an active High clock enable for the data path.
All parallel 3-state signals enter the OSERDES module through ports T1 to T4. The ports
are connected to the FPGA fabric, and can be configured as one, two, or four bits.
1 (each)
Width
1
1
1
1
1
1
for bit ordering at the inputs and output of the OSERDES along with the
Output data clock enable.
Reverse SR pin. Not available in the OSERDES block; connect to GND.
Carry input for data width expansion. Connect to SHIFTOUT1 of slave
OSERDES. See
Carry input for data width expansion. Connect to SHIFTOUT2 of slave
OSERDES. See
Active High reset.
Parallel 3-state inputs.
3-state clock enable.
www.xilinx.com
“OSERDES Width
“OSERDES Width
“OSERDES Width
Output Parallel-to-Serial Logic Resources (OSERDES)
Expansion”.
Expansion”.
Description
Expansion”). Refer to
Figure 8-3,
389