XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 209

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 5-6: Distributed RAM Timing Parameters
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Sequential Delays for Slice LUT Configured as RAM (Distributed RAM)
T
T
Setup and Hold for Slice LUT Configured as RAM (Distributed RAM)
T
T
T
T
T
Clock CLK
T
Parameter
AS
SHCKO
SHCKOF5
xS
xH
DS
WS
WC
/T
/T
= Setup time (before clock edge)
/T
= Hold time (after clock edge)
AH
DH
WH
R
CLK to X
CLK to F5 output (WE
active)
BX/BY configured as data
input (DI)
F/G Address inputs
WE input (SR)
Distributed RAM Timing Parameters
Distributed RAM Timing Characteristics
Function
Table 5-6
of the paths in
The timing characteristics of a 16-bit distributed RAM implemented in a Virtex-4 FPGA
slice (LUT configured as RAM) are shown in
DATA_OUT
X/XMUX
Output
ADDR
shows the timing parameters for the distributed RAM in SLICEM for a majority
CLK
WE
DI
Figure 5-23: Slice Distributed RAM Timing Characteristics
Figure
1
Time after the Clock (CLK) of a Write operation that the data written to the
distributed RAM is stable on the X output of the slice.
Time after the Clock (CLK) of a Write operation that the data written to the
distributed RAM is stable on the F5 output of the slice.
The following descriptions are for setup times only.
Time before the clock that data must be stable at the BX/BY input of the
slice.
of the slice LUT (configured as RAM).
input of the slice LUT (configured as RAM).
Minimum clock period to meet address write cycle time.
Time before the clock that address signals must be stable at the F/G inputs
Time before the clock that the write enable signal must be stable at the WE
T
WPH
1
WRITE
T
T
T
5-22.
T
AS
WS
DS
WC
2
T
T
/T
SHCKO
1
WPL
www.xilinx.com
CYCK
2
T
ILO
READ
X
F
MEM(F)
3
WRITE
0
3
Figure
0
Description
4
5-23.
WRITE
4
1
1
5
CLB / Slice Timing Models
WRITE
0
5
0
6
T
X
READ
ILO
UG070_5_23_080204
E
MEM(E)
7
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