XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 224

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
224
Attributes
Location Constraints
Content Initialization - INIT
The INIT attribute defines the initial shift register contents. The INIT attribute is a hex-
encoded bit vector with four digits (0000).The left-most hexadecimal digit is the most
significant bit. By default the shift register is initialized with all zeros during the device
configuration sequence, but any other configuration value can be specified.
Each CLB resource has four slices: S0, S1, S2, and S3. As an example, in the bottom left CLB
resource, each slice has the coordinates shown in
Table 5-15: Slice Coordinates in the Bottom-Left CLB Resource
To constrain placement, shift register instances can have LOC properties attached to them.
Each 16-bit shift register fits in one LUT.
A 32-bit shift register in static or dynamic address mode fits in one slice (two LUTs and one
MUXF5). This shift register can be placed in SLICEM only.
A 64-bit shift register in static or dynamic address mode fits in two slices. These slices are
S0 and S2.
The dedicated CLB shift chain runs from the top slice to the bottom slice. The data input
pin must either be in slice S0 or in S2. The address selected as the output pin (Q) is the
MUXF6 output.
Slice S3
X1Y1
Figure 5-30
D
illustrates the position of the four LUTs in a CLB resource.
LUT
LUT
LUT
LUT
Figure 5-30: Shift Register Placement
www.xilinx.com
Slice S2
X0Y1
Q63
F5
F5
Slice S2
Slice S0
F6
a
Table
Slice S1
X1Y0
5-15.
SRLC64E
(output SRLC64E)
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
UG070_5_30_122205
CLB
Slice S0
X0Y0
R