XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 121

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
CLK
WE
EN
Optional
Inverter
Independent Read and Write Port Width Selection
Cascadable Block RAM
R
Address
DI
Register
All block RAM ports have control over data width and address depth (aspect ratio).
Virtex-4 devices extend this flexibility to each individual port where Read and Write can be
configured with different data widths. See
If the Read port width differs from the Write port width, and is configured in
WRITE_FIRST mode, then DO shows valid new data only if all the write bytes are enabled.
Independent Read and Write port width selection increases the efficiency of implementing
a content addressable memory (CAM) in block RAM. Excluding the built-in FIFO, this
option is available for all RAM port sizes and modes.
Combining two 16K x 1 RAMs to form one 32K x 1 RAM is possible in the Virtex-4 block
RAM architecture without using local interconnect or additional CLB logic resources.
NO_CHANGE mode is not supported in 32K x 1 RAM configuration. Any two adjacent
block RAMs can be cascaded to generate a 32K x 1 block RAM. Increasing the depth of the
block RAM by cascading two block RAMs is available only in the 32K x 1 mode. Further
information on cascadable block RAM is described in the
Design Considerations”
Larger RAM Structures
ports connected in the Cascadable mode. The
Devices”
Figure 4-5: Block RAM Logic Diagram (One Port Shown)
Strobe
Write
section includes further information on cascadable block RAMs.
(common to
both ports)
Memory
Array
Read
Strobe
section.
section. For other wider and/or deeper sizes, consult the
www.xilinx.com
Control Engine
Figure 4-6
Additional Block RAM Features in Virtex-4 Devices
D
Latches
Latch
Enable
Q
shows the block RAM with the appropriate
“Block RAM Attributes,” page
Configurable Options
“Additional Block RAM Features in Virtex-4
Optional
Inverter
“Additional RAMB16 Primitive
D
Register
Q
127.
DO
UG070_4_05_030708
Creating
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