XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 386

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
Output Parallel-to-Serial Logic Resources (OSERDES)
386
Data Parallel-to-Serial Converter
Clock Event 4
The first two bits of the fourth word CD have been sampled into the input side registers of
the ISERDES.
On this same edge of CLKDIV, the second word sampled is presented to Q1–Q4 with one
bit shifted to the right. The actual bits from the input stream that appear at the Q1–Q4
outputs during this cycle are shown in B of
The realigned bits on Q1–Q4 are sampled into the FPGA fabric on the CLKDIV domain.
The total latency from when the ISERDES captures the asserted Bitslip input to when the
realigned ISERDES outputs Q1–Q4 are sampled by CLKDIV is 2 CLKDIV cycles.
Clock Event 5
The third word sampled is presented to Q1–Q4 with three bits shifted to the left. The actual
bits from the input stream that appear at the Q1–Q4 outputs during this cycle are shown in
C of
The Virtex-4 FPGA OSERDES is a dedicated parallel-to-serial converter with specific
clocking and logic resources designed to facilitate the implementation of high-speed
source-synchronous interfaces. Every OSERDES module includes a dedicated serializer for
data and 3-state control. Both Data and 3-state serializers can be configured in SDR and
DDR mode. Data serialization can be up to 6:1 (10:1 if using
Expansion”). 3-state serialization can be up to 4:1.
Figure 8-14
components and features of the block.
The data parallel-to-serial converter in one OSERDES blocks receives two to six bits of
parallel data from the fabric (10:1 if using
data, and presents it to the IOB via the OQ outputs. Parallel data is serialized from lowest
Figure
CLKDIV
T1 - T4
TCE
D1 - D6
OCE
CLK
SR
8-13.
shows a block diagram of the OSERDES, highlighting all the major
Parallel-to-Serial Converter
Parallel-to-Serial Converter
Figure 8-14: OSERDES Block Diagram
www.xilinx.com
3-State
Data
“OSERDES Width
Figure
8-13.
OQ
TQ
“OSERDES Width
UG070 (v2.6) December 1, 2008
Expansion”), serializes the
Output Driver
Virtex-4 FPGA User Guide
IOB
ug070_10_041007
R