XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 154

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
FIFO VHDL and Verilog Templates
154
FIFO VHDL Template
The ALMOSTFULL and ALMOSTEMPTY offsets can also be used in unstoppable block
transfer applications to signal that a new block of data can be written or read.
When setting the offset ranges in the design tools, use hexadecimal notation.
VHDL and Verilog templates are available in the Libraries Guide. Also see section
Error Condition and Work-Arounds,” page
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Library UNISIM;
use UNISIM.vcomponents.all;
--
-- FIFO16: Virtex-4 Block RAM Asynchronous FIFO
-- Virtex-4 FPGA User Guide
FIFO16_inst : FIFO16
generic map (
port map (
declaration
<--Cut code below this line and paste into the architecture body-->
declaration
Copy the following two statements and paste them before the
Entity declaration, unless they already exists.
instance
primitives : Xilinx primitives and points to the models that will
Library
ALMOST_EMPTY_OFFSET => X"000", -- Sets the almost empty threshold
Xilinx
FIFO16
ALMOST_FULL_OFFSET => X"000",
DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36
FIRST_WORD_FALL_THROUGH => FALSE)
ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit almost empty output flag
ALMOSTFULL => ALMOSTFULL,
DO => DO,
DOP => DOP,
EMPTY => EMPTY,
FULL => FULL,
RDCOUNT => RDCOUNT,
RDERR => RDERR,
WRCOUNT => WRCOUNT,
WRERR => WRERR,
DI => DI,
DIP => DIP,
VHDL
code
for
: the architecture body of the design code. The instance
: In addition to adding the instance declaration, a use
: following instance declaration needs to be placed in
: after the "=>" assignment can be changed to properly
: library contains the component declarations for all
: statement for the UNISIM.v components library needs
: To incorporate this function into the design, the
: name (FIFO16_inst) and/or the port declarations
: connect this function to the design. All inputs and
: outputs must be connected.
: to be added before the entity declaration. This
: be used for simulation.
www.xilinx.com
165.
-- 1-bit almost full output flag
-- 32-bit data output
-- 4-bit parity data output
-- 1-bit empty output flag
-- 1-bit full output flag
-- 12-bit read count output
-- 1-bit read error output
-- 12-bit write count output
-- 1-bit write error
-- 32-bit data input
-- 4-bit partity input
-- Sets almost full threshold
-- Sets the FIFO FWFT to TRUE or FALSE
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
“FIFO16
R