XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 122

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
122
FIFO Support
The block RAM can be configured as an asynchronous FIFO (different clock on read and
write ports) or a synchronous FIFO. In the FIFO mode, the block RAM Port A is the FIFO
read port, while the block RAM Port B is the FIFO write port. The supported
configurations are: 4K x 4, 2K x 9, 1K x 18, and 512 x 36.
I/Os used for the FIFO implementation. The
further details.
Interconnect
WE[3:0]
WE[3:0]
A[13:0]
A[13:0]
A14
A14
WR_CLK
RD_CLK
DI
DI
WR_EN
RD_EN
SSR
DI
Block RAM
RAM_EXTENSION =
RAM_EXTENSION =
Figure 4-7: Block RAM Implemented as a FIFO
LOWER(1)
UPPER(0)
0
1
0
1
Figure 4-6: Cascadable Block RAM
I/Os not used
www.xilinx.com
in FIFO Mode
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
DIA
AA[13:0]
WEA[3:0]
ENA
SSRA
DIB
AB[13:0]
WEB[3:0]
ENB
SSRB
CLKA
CLKB
DI
A[13:0]
A14
WE
DI
A[13:0]
A14
WE
“Built-in FIFO Support”
Port A
Port B
FIFO
Logic
DOA
DOB
Connect to logic High or Low
D0
D0
CASCADEOUT
(No Connect)
CASCADEIN
Figure 4-7
CASCADEIN of Top
CASCADEOUT of Bottom
UG070 (v2.6) December 1, 2008
1
0
1
0
Virtex-4 FPGA User Guide
UG070_4_07_071204
DO
EMPTY
ALMOST_EMPTY
FULL
ALMOST_FULL
RDCOUNT
WRCOUNT
shows the block RAM
Output FF
Optional
Output FF
section contains
UG070_4_06_033005
D0
D0
Not Used
R