XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 94

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
DCM Timing Models
94
CLKFX180
LOCKED
CLK180
CLKDV
CLKFX
CLK90
CLKIN
CLK0
RST
Reset/Lock
The following timing diagrams describe the behavior of the DCM clock outputs under four
different conditions.
1.
2.
3.
4.
In
clocks are stabilized to the desired values, and the LOCKED signal is asserted.
•
•
•
Figure
Reset/Lock
Fixed-Phase Shifting
Variable-Phase Shifting
Status Flags
Prior to Clock Event 1
Prior to clock event 1, the DCM is locked. All clock outputs are in phase with the
correct frequency and behavior.
Clock Event 1
Some time after clock event 1 the reset signal is asserted at the (RST) pin. While reset is
asserted, all clock outputs become a logic zero. The reset signal is an asynchronous
reset. Note: the diagram is not shown to scale. For the DCM to operate properly, the
reset signal must be asserted for at least 200 ms.
Clock Event 2
Clock event 2 occurs a few cycles after reset is asserted and deasserted. At clock event
2, the lock process begins. At time LOCK_DLL, after clock event 2, if no fixed phase
shift was selected then all clock outputs are stable and in phase. LOCKED is also
asserted to signal completion.
2-20, the DCM is already locked. After the reset signal is applied, all output
Figure 2-20: RESET/LOCK Example
1
200 ms
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2
LOCK
DLL
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
UG070_2_19_031208
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