XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 140

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
140
Cascadable Block RAM
Byte-Write Enable
1.
2.
3.
4.
5.
To use the cascadable block RAM feature:
1.
2.
3.
4.
5.
6.
Figure 4-6
The following rules should be considered when the following when using the byte-write
enable feature:
•
•
•
Figure 4-8
If the DI[A|B] pins are less than 32 bits wide, concatenate (32 – DI_BIT_WIDTH) logic
zeros to the front of DI[A|B].
If the DIP[A|B] pins are less than 4 bits wide, concatenate (4 – DIP_BIT_WIDTH) logic
zeros to the front of DIP[A|B]. DIP[A|B] is unconnected when not in use.
DO[A|B] pins must be 32 bits wide. However, valid data are only found on pins 0 to
DO_BIT_WIDTH.
DOP[A|B] pins must be 4 bits wide. However, valid data are only found on pins 0 to
DO_BIT_WIDTH. DOP[A|B] is unconnected when not in use.
ADDR[A|B] pins must be 15 bits wide. However, valid addresses for non-cascadable
block RAM are only found on pins 13 to (14 – address width). The remaining pins,
including pin 14, should be tied High.
Two RAMB16 primitives must be instantiated.
Set the RAM_EXTENSION_A and RAM_EXTENSION_B attribute for one RAMB16 to
UPPER, and another to LOWER.
Connect the upper RAMB16’s CASCADEINA and CASCADEINB ports to the
CASCADEOUTA and CASCADEOUTB ports of the lower RAMB16. The
CASCADEOUT ports for the upper RAMB16 do not require a connection. Connect the
CASCADEIN ports for the lower RAMB16 to either logic High or Low.
The data output ports of the lower RAMB16 are not used. These pins are unconnected.
If placing location constraints on the two RAMB16s, they must be adjacent. If no
location constraint is specified, the ISE software will automatically manage the
RAMB16 locations.
The address pins ADDR[A|B] must be 15 bits wide. Both read and write ports must be
one bit wide.
In x36 mode, WE[3:0] is connected to the four user WE inputs.
In x18 mode, WE[0] and WE[2] are connected and driven by the user WE[0], while
WE[1], and WE[3] are driven by the user WE[1].
In x9, x4, x2, x1, WE[3:0] are all connected to a single user WE.
shows the cascadable block RAM.
shows a byte-write enabled block RAM.
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UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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