XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 37

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
CE
I0
I1
O
S
1
at I0
R
T
BCCKO_O
BUFGMUX_VIRTEX4 with a Clock Enable
A BUFGMUX_VIRTEX4 with a clock enable BUFGCTRL configuration allows the user to
choose between the incoming clock inputs. If needed, the clock enable is used to disable
the output.
shows the timing diagram.
In
•
•
•
•
Figure 1-16: BUFGMUX_VIRTEX4 with a CE Timing Diagram
Figure
At time event 1, output O uses input I0.
Before time event 2, S is asserted High.
At time T
to Low transition of I0 followed by a High to Low transition of I1 is completed.
At time T
switched Low and kept at Low after a High to Low transition of I1 is completed.
CE
1-16:
I1
I0
S
Figure 1-15
Figure 1-15: BUFGMUX_VIRTEX4 with a CE and BUFGCTRL
BUFGMUX_VIRTEX4+CE
BCCKO_O
BCCCK_CE
2
Design Example
Begin I1
, after time event 2, output O uses input I1. This occurs after a High
, before time event 3, CE is asserted Low. The clock output is
illustrates the BUFGCTRL usage design example and
T
www.xilinx.com
BCCKO_O
O
CE
S
GND
GND
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Clock Off
Global Clocking Resources
3
ug070_1_15_071304
T
BCCCK_CE
Figure 1-16
O
UG070_1_16_082504
37