XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 179

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XC4VFX60-11FFG672I

Manufacturer Part Number
XC4VFX60-11FFG672I
Description
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX60-11FFG672I

Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Total Ram Bits
4276224
Number Of I /o
352
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-BBGA, FCBGA
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Block RAM ECC Primitive
Block RAM ECC Port Description
R
Figure 4-35
Table 4-17
Table 4-17: Block RAM ECC Port Names and Descriptions
Notes:
1. Hamming code implemented in the block RAM ECC logic detects one of three conditions: no
WRADDR<8:0>
STATUS<1:0>
RDADDR<8:0>
detectable error, single-bit error detected and corrected on DO (but not corrected in the memory), and
double-bit error detected without correction. The result of STATUS<1:0> indicates these three
conditions.
Port Name
DO<63:0>
DI<63:0>
WRCLK
RDCLK
WREN
RDEN
SSR
lists and describes the block RAM ECC I/O port names.
shows RAMB32_S64_ECC, the block RAM ECC primitive.
Figure 4-35: RAMB32_S64_ECC: Block RAM ECC Primitive
(1)
Direction
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
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DI<63:0>
WRADDR<8:0>
RDADDR<8:0>
WREN
RDEN
S S R
WRCLK
RDCLK
Data input bus
Write address bus
Read address bus
Write enable. When WREN = 1, data will be written into
memory. When WREN = 0, write is disabled
Read enable. When RDEN = 1, data will be read from
memory. When RDEN = 0, read is disabled
Not supported when using the block RAM ECC primitive.
Always connect to GND.
Clock for write operations
Clock for read operations
Data output bus
Error status bus
RAMB32_S64_ECC
Built-in Block RAM Error Correction Code
STATUS<1:0>
DO<63:0>
Signal Description
ug070_4_ECC_022204
179

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