XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 314

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
Table 6-43: Equivalent V
314
Notes:
1. These numbers are based on the package files and device pinout. Some of the numbers are not integers as these banks share their
2. Bank 0 in all devices contains no user I/O. Therefore, SSO analysis is unnecessary for Bank 0.
3. Banks 9 and 10 are not available in the XC4VFX12 device.
Virtex-4 FPGA (LX/FX Families)
SF363
FF668
Virtex-4 FPGA (SX Family)
FF668
GND pin with other banks. Most of the limitations are based on the availability of GND pins in the vicinity of the bank. There are a
few instances where the limitation is due to V
Package
Actual SSO Limits versus Nominal SSO Limits
Electrical Basis of SSO Noise
Equivalent V
0
1
2
2
Table 6-42: Non-Sparse Chevron Simultaneously Switching Output Limits per
Equivalent V
Since ground pins and V
the number of effective V
physical V
pin pairs in each bank of each non-sparse chevron package. Some of the numbers are not
integers as these banks share GND pins with other resources.
The Virtex-4 FPGA SSO limits are defined in for a set of nominal system conditions in
Table 6-40
automated
the user to account for differences between actual and nominal PCB power systems,
receiver capacitive loading, and maximum allowable ground bounce or V
spreadsheet calculator,
Power supply disturbance can take the form of ground bounce or V
usually a combination of the two. This bounce is a deviation of the die supply voltage (die
GND rail or die V
GND rail or PCB V
Voltage
0.5
CCO
1
2
2
3.3V
/GND Pairs per Bank: Non-Sparse Chevron
0.5
2
2
2
CCO
CCO
and
“Parasitic Factors Derating Method (PFDM)”
GTL
GTL_DCI
GTLP
GTLP_DCI
CCO
3
1
2
2
/GND pin pairs.
/GND Pairs: Non-Sparse Chevron
Table
/GND Pair (Continued)
CCO
CC
CC
4
1
2
2
6-42. To compute the actual limits for a specific user's system, the
rail) with respect to the voltage of the associated PCB supply (PCB
pins.
IOStandard
rail). The deviation of die supplies from PCB supplies comes from
“Full Device SSO
4.5
4.5
4.5
CCO
5
CCO
www.xilinx.com
pins are connected to common structures inside the package,
/GND pin pairs in a bank can differ from the number of
4.5
6
5
5
Table 6-43
Bank Number
7
3
5
5
Calculator”, automates this process.
8
3
4
4
shows the number of equivalent V
4
4
4
4
3
---
9
3
(3)
3
10
---
3
(3)
SF363 and FF668 Packages
Non-Sparse Chevron Limit
must be used. The PFDM allows
11
---
---
---
UG070 (v2.6) December 1, 2008
12
---
---
---
Virtex-4 FPGA User Guide
CC
13
---
---
---
bounce, and is
CC
14
---
---
---
bounce. A
CCO
15
---
---
---
/GND
16
---
---
---
R