XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 228

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
228
Multiplexer Primitives and Submodules
Port Signals
Data In - DATA_I
Control In - SELECT_I
Four primitives are available for access to the dedicated MUXFX in each slice. In the
example shown in
Table 5-16: MUXFX Resources
In addition to the primitives, five submodules to implement multiplexers from 2:1 to 32:1
are provided in VHDL and Verilog code. Synthesis tools can automatically infer these
primitives (MUXF5, MUXF6, MUXF7, and MUXF8); however, the submodules described
in this section use instantiation of the new MUXFX to guarantee an optimized result.
Table 5-17
Table 5-17: Available Submodules
The data input provides the data to be selected by the SELECT_I signal(s).
The select input signal or bus determines the DATA_I signal to be connected to the output
DATA_O. For example, the MUX_4_1_SUBM multiplexer has a 2-bit SELECT_I bus and a
4-bit DATA_I bus.
Table 5-18: Selected Inputs
MUXF5
MUXF6
MUXF7
MUXF8
MUX_2_1_SUBM
MUX_4_1_SUBM
MUX_8_1_SUBM
MUX_16_1_SUBM
MUX_32_1_SUBM
Primitive
Submodule
lists available submodules.
SELECT_I[1:0]
S0, S1, S2, S3
S0, S1
S2
S3
0 0
0 1
1 0
1 1
Table 5-18
Table
Slice
5-16, MUXF7 is available only in slice S2.
Multiplexer
www.xilinx.com
16:1
32:1
shows the DATA_I selected for each SELECT_I value.
2:1
4:1
8:1
S
S
S
S
Control
DATA_I[0]
DATA_I[1]
DATA_I[2]
DATA_I[3]
SELECT_I
SELECT_I[1:0]
SELECT_I[2:0]
SELECT_I[3:0]
SELECT_I[4:0]
Control
I0, I1
I0, I1
I0, I1
I0, I1
DATA_I[1:0]
DATA_I[3:0]
DATA_I[8:0]
DATA_I[15:0]
DATA_I[31:0]
Input
DATA_O
UG070 (v2.6) December 1, 2008
Input
Virtex-4 FPGA User Guide
O
O
O
O
DATA_O
DATA_O
DATA_O
DATA_O
DATA_O
Output
Output
R