XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 372

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
Table 8-2: ISERDES Attributes
372
BITSLIP_ENABLE
DATA_RATE
DATA_WIDTH
INTERFACE_TYPE
IOBDELAY
IOBDELAY_TYPE
IOBDELAY_VALUE
NUM_CE
SERDES_MODE
Attribute Name
ISERDES Attributes
BITSLIP_ENABLE Attribute
DATA_RATE Attribute
DATA_WIDTH Attribute
Allows the user to use the Bitslip submodule
or bypass it.
Enables incoming data stream to be
processed as SDR or DDR data.
Defines the width of the serial-to-parallel
converter. The legal value depends on the
DATA_RATE attribute (SDR or DDR).
Chooses the ISERDES use model.
Applies delay to combinatorial or registered
paths, both, or neither.
Sets the type of delay. See
Element
Specifies the initial delay. See
Element
Defines the number of clock enables.
Defines whether the ISERDES module is a
master or slave when using width expansion.
Table 8-2
attribute follows the table. For more information on applying these attributes in UCF,
VHDL, or Verilog code, refer to the Xilinx® ISE® Software Manual.
The BITSLIP_ENABLE attribute enables the Bitslip submodule. The possible values are
TRUE and FALSE (default). BITSLIP_ENABLE must be set to TRUE when
INTERFACE_TYPE is NETWORKING and FALSE when INTERFACE_TYPE is MEMORY.
When set to TRUE, the Bitslip submodule responds to the BITSLIP signal. When set to
FALSE, the Bitslip submodule is bypassed. See
The DATA_RATE attribute defines whether the incoming data stream is processed as
single data rate (SDR) or double data rate (DDR). The allowed values for this attribute are
SDR and DDR. The default value is DDR.
The DATA_WIDTH attribute defines the parallel data output width of the serial-to-parallel
converter. The possible values for this attribute depend on the INTERFACE_TYPE and
DATA_RATE attributes. See
(IDELAY)”.
(IDELAY)”.
summarizes all the applicable ISERDES attributes. A detailed description of each
Description
“Input Delay
www.xilinx.com
“Input Delay
Table 8-3
for allowable data widths.
Boolean: “TRUE” or “FALSE”
String: “SDR” or “DDR”
Integer: 2, 3, 4, 5, 6, 7, 8, or 10.
If DATA_RATE = DDR, value is
limited to 4, 6, 8, or 10.
If DATA_RATE = SDR, value is
limited to 2, 3, 4, 5, 6, 7, or 8.
String: “MEMORY” or
“NETWORKING”
String: “NONE”, “IBUF”, “IFD”,
or “BOTH”
String: “DEFAULT”, “FIXED”,
or “VARIABLE”
Integer: 0 to 63
Integer: 1 or 2
String: “MASTER” or “SLAVE”
“BITSLIP
Value
Submodule”.
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
MEMORY
DEFAULT
MASTER
Default
FALSE
NONE
Value
DDR
4
0
2
R