XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 172

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
172
FASTCLK (400 MHz)
WREN (From User)
WRCLK (125 MHz)
WM
Writ
Wr
Notes:
Timing Diagram
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The timing diagram for the worst-case write condition is shown in
diagram depicts two back-to-back FIFO write cycles. This is a “worst-case” diagram,
because the rising edge of WRCLK slightly trails the rising edge of FASTCLK when write
enable (WREN) is TRUE. Please refer to
asynchronous to FASTCLK and the leading edge of WM might be metastable. FASTCLK
and WRCLK depictions are drawn to scale, relative to each other.
The Read timing is similar to the Write timing shown in
The ALMOSTEMPTY flag is delayed from 1 to 2 RDCLK periods after the condition is
detected.
The ALMOSTFULL flag is delayed from 1 to 2 WRCLK periods after the condition is
detected.
The DCM generating the FASTCLK clock must be locked before the FIFOs can be
used. (The STARTUP_WAIT attribute can be used to make sure that the DCMs are
locked before the configuration is done.)
The FASTCLK clock must be continuously available when any of the FIFOs in the
system are being used. (Monitor the LOCK signals from all the DCMs to make sure
that the FASTCLK clock is running. If LOCK goes Low, the DCMs should be reset.)
For this design to work properly the maximum words in the FIFO16 must never
exceed the nominal maximum - 3; e.g., a 512 word FIFO must never contain more than
509 words.
This work-around does not currently provide a FULL flag. However, the EMPTY flag
from the FIFO16 can be used.
Figure 4-30: Write Timing Diagram
www.xilinx.com
Figure 4-27
for signals Wr and WM. Signal Wr is
Figure
UG070 (v2.6) December 1, 2008
4-30.
Virtex-4 FPGA User Guide
Figure
4-30. The
UG070_c4_31_020307
R