XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 294

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
294
Differential Termination: DIFF_TERM Attribute
LVDS and Extended LVDS (Low Voltage Differential Signaling)
Table 6-31
Table 6-31: Allowed Attributes for the SSTL I/O Standards
Table 6-32: Allowed Attributes for the DIFF_SSTL I/O Standards
Virtex-4 FPGA IOBs provide a 100Ω differential termination across the input differential
receiver terminals. This attribute is used in conjunction with LVDS_25, LVDSEXT_25,
LDT_25, and ULVDS_25. It replaces the Virtex-II Pro FPGA LVDS_25_DT,
LVDSEXT_25_DT, LDT_25_DT, and ULVDS_25_DT.
The on-chip input differential termination in Virtex-4 devices provides major advantages
over the external resistor by removing the stub at the receiver completely and therefore
greatly improving signal integrity:
•
•
•
The V
differential termination. DIFF_TERM is only available for inputs and can only be used with
a bank voltage of V
section outlines using this feature.
Low Voltage Differential Signaling (LVDS) is a very popular and powerful high-speed
interface in many system applications. Virtex-4 FPGA I/Os are designed to comply with
the EIA/TIA electrical specifications for LVDS to make system and board design easier.
With the use of an LVDS current-mode driver in the IOBs, the need for external source
termination in point-to-point applications is eliminated, and with the choice of an
extended mode, Virtex-4 devices provide the most flexible solution for doing an LVDS
design in an FPGA.
Extended LVDS provides a higher drive capability and voltage swing (350 - 750 mV),
making it ideal for long-distance or cable LVDS links. The output AC characteristics of the
LVDS extended mode driver are not within the EIA/TIA specifications. The LVDS
extended mode driver is intended for situations requiring higher drive capabilities to
produce an LVDS signal within the EIA/TIA specification at the receiver.
IOSTANDARD
CAPACITANCE
IOSTANDARD
CAPACITANCE
Consumes less power than DCI termination
Does not use VRP/VRN pins (DCI)
Supports LDT and ULVDS (not supported by DCI termination)
CCO
Attributes
Attributes
details the allowed attributes that can be applied to the SSTL I/O standards.
of the I/O bank must be connected to 2.5V ±5% to provide 100Ω of effective
CCO
= 2.5V. The
www.xilinx.com
IBUFDS/IBUFGDS
IBUFDS/IBUFGDS
“Differential Termination Attribute”
All possible DIFF_SSTL standards
LOW, NORMAL, DONT_CARE
LOW, NORMAL, DONT_CARE
All possible SSTL standards
OBUFDS/OBUFTDS
OBUFDS/OBUFTDS
Primitives
Primitives
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
(DIFF_TERM)
IOBUFDS
IOBUFDS
R