XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 165

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

FIFO16 Error Condition and Work-Arounds
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
FIFO16 Error Condition
Solution 1: Synchronous/Asynchronous Clock Work-Arounds
R
Synchronous Clock Work-Around
The FIFO16 flags (ALMOSTFULL, FULL, ALMOSTEMPTY, EMPTY), after a very specific
sequence of events, transition into a state in which they operate incorrectly. Erroneous
settings of the FULL and EMPTY flags can jeopardize even basic FIFO functionality. This
section details the error condition and describes synchronous and asynchronous clock
work-arounds available to ensure robust operation under all operating conditions. Three
different solutions are described in this section. The solution summary section lists the
criteria to be used while choosing a particular solution.
The basic Virtex-4 FPGA FIFO16 ceases to correctly generate the ALMOSTEMPTY and
EMPTY flags, after the following sequence occurs:
1.
2.
A similar sequence of operations around the ALMOST_FULL_OFFSET ceases to generate
correct ALMOSTFULL and FULL flags.
In a synchronous design, simultaneous operation can be avoided by offsetting the read and
write clocks by about 1 ns. This is easily achieved by using opposite clock edges for the
read and write clocks. In most applications, this requires data resynchronization registers
to bring read and write back together in the same clock domain.
concept.
This resynchronization must be done on the input side so that the critical EMPTY flag
avoids any latency. The FULL flag is eliminated, as it would not be useful with its 2-clock
latency; ALMOSTFULL should be used instead. The connections between the input
registers and the FIFO16 must be tightly constrained, as this part of the circuit effectively
runs at twice the clock rate.
A sequence of read and/or write operations makes the number of words in the FIFO
equal to the ALMOST_EMPTY_OFFSET threshold (either coming from a higher level
as a result of a read operation, or from a lower level as a result of a write operation).
This is then followed by either a write or a read operation.
If (and only if) the operation immediately following this particular read or write
operation is a simultaneous read/write operation, where the enabled read and write
active clock edges are coincident or very close (<500 ps) together, the ALMOSTEMPTY
flag is incorrect. Since ALMOSTEMPTY is a condition for decoding EMPTY, the
EMPTY flag is also wrong.
ALMOSTFULL
WRERR
WREN
DI/DIP
CLK
Figure 4-24: Synchronous Clock Work-Around
www.xilinx.com
CLKbar
CLK
FIFO16 Error Condition and Work-Arounds
wdat
wren
wrclk
full
afull
wrerr
FIFO16
aempty
empty
rdclk
rderr
rden
rdat
Figure 4-24
DO/DOP
RDEN
CLK
EMPTY
ALMOSTEMPTY
RDERR
UG070_c4_25_020307
illustrates the
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