XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 78

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
78
Phase-Shift Examples
The following usage examples take both the PHASE_SHIFT attribute and the
FINE_SHIFT_RANGE components into consideration:
•
•
•
•
If the phase shift is limited by the FINE_SHIFT_RANGE, use the coarse-grained phase
shift to extend the phase-shift range or set DCM_PERFORAMANCE_MODE attribute to
MAX_RANGE to increase the FINE_SHIFT_RANGE.
CLK180, and CLK270 outputs assuming FINE_SHIFT_RANGE = 10 ns.
In variable mode, the phase-shift factor is changed by activating PSEN for one period of
PSCLK. At the PSCLK clock cycle where PSEN is activated, the level of PSINCDEC input
determines whether the phase-shift increases or decreases. A High on PSINCDEC
increases the phase shift, and a Low decreases the phase shift.
After the deskew circuit increments or decrements, the signal PSDONE is asserted High
for a single PSCLK cycle. This allows the next change to be performed.
The user interface and the physical implementation are different. The user interface
describes the phase shift as a fraction of the clock period (N/256). The physical
implementation adds the appropriate number of buffer stages (each DCM_TAP) to the
clock delay. The DCM_TAP granularity limits the phase resolution at higher clock
frequencies.
For frequency ≥ 100 MHz (period ≤ 10 ns)
CLK0 PHASE_SHIFT = 0 - 255 covers the
whole range of period.
For frequency between 50 - 100 MHz
(period 10 - 20 ns). At 50 MHz, use
CLK0 PHASE_SHIFT= 0 - 127 for the
first 10 ns.
Use CLK180 with PHASE_SHIFT= 0 - 127
for the next 10 ns.
For frequency between 25 - 50 MHz
(period 20 - 40 ns). At 25 MHz, use
CLK0 PHASE_SHIFT= 0 - 63 for the
first 10 ns.
Use CLK90 with PHASE_SHIFT= 0 - 63
for the next 10 ns.
Use CLK180 with PHASE_SHIFT= 0 - 63
for the next 10 ns.
Use CLK270 with PHASE_SHIFT= 0 - 63
for the last 10 ns.
If PERIODCLKIN = 2 × FINE_SHIFT_RANGE, then the PHASE_SHIFT in fixed mode
is limited to ±128. In variable-positive mode, PHASE_SHIFT is limited to +128. In
variable-center mode the PHASE_SHIFT is limited to ±64.
If PERIODCLKIN = FINE_SHIFT_RANGE, then the PHASE_SHIFT in variable-
positive mode is limited to +255. In fixed and variable-center mode the
PHASE_SHIFT is limited to ±255.
If PERIODCLKIN ≤ FINE_SHIFT_RANGE, then the PHASE_SHIFT in variable-
positive mode is limited to +255. In fixed and variable-center mode the
PHASE_SHIFT is limited to ±255.
For all previously described cases, the direct mode is always limited to +1023.
Figure 2-6: Fixed Phase-Shift Examples
www.xilinx.com
CLK180(50 MHz)
CLK180(25 MHz)
CLK270(25 MHz)
CLK0(100 MHz)
CLK90(25 MHz)
CLK0(25 MHz)
CLK0(50 MHz)
10 ns
Figure 2-6
UG070 (v2.6) December 1, 2008
10 ns
illustrates using CLK90,
Virtex-4 FPGA User Guide
10 ns
UG070_2_05_031208
10 ns
R