XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 213

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Slice Carry-Chain Timing Model and Parameters
R
Clock Event 1: Shift_In
During a Write (Shift_In) operation, the single-bit content of the register at the address on
the ADDR inputs is changed, as data is shifted through the SRL. The data written to this
register is reflected on the X/Y outputs synchronously, if the address is unchanged during
the clock event. If the ADDR inputs are changed during a clock event, the value of the data
at the addressable output (D) is invalid.
•
•
Clock Event 2: Shift_In
•
Clock Event 3: Shift_In/Addressable (Asynchronous) READ
All Read operations are asynchronous to the CLK signal. If the address is changed
(between clock events), the contents of the register at that address are reflected at the
addressable output (X/Y outputs) after a delay of length T
a LUT).
•
•
Clock Event 16: MSB (Most Significant Bit) Changes
At time T
0 in this case) on the XB output of the slice via the MC15 output of the LUT (SRL). This is
also applicable for the XMUX, YMUX, XB, YB, C
T
Figure 5-26
FPGA slice have been omitted for clarity. Only the elements relevant to the timing paths
described in this section are shown.
WOSX
At time T
enabling the SRL for the Write operation that follows.
At time T
and is reflected on the X/Y output after a delay of length T
Since the address 0 is specified at clock event 1, the data on the DI input is reflected at
the D output, because it is written to register 0.
At time T
and is reflected on the X/Y output after a delay of length T
Since the address 0 is still specified at clock event 2, the data on the DI input is
reflected at the D output, because it is written to register 0.
At time T
and is reflected on the X/Y output T
The address is changed (from 0 to 2) some time after clock event 3. The value stored in
register 2 at this time is a 0 (in this example, this was the first data shifted in), and it is
reflected on the X/Y output after a delay of length T
, T
REGXB
WOSXB
illustrates a carry-chain in a Virtex-4 FPGA slice. Some elements of the Virtex-4
WSS
DS
DS
DS
, and T
after clock event 16, the first bit shifted into the SRL becomes valid (logical
before clock event 1 the data becomes valid (0) at the DI input of the SRL
before clock event 2, the data becomes valid (1) at the DI input of the SRL
before clock event 3 the data becomes valid (1) at the DI input of the SRL,
before clock event 1, the write-enable signal (SR) becomes valid-High,
WOSYB
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after clock event 16.
REG
time after clock event 3.
OUT
, and F5 outputs at time T
ILO
ILO
.
CLB / Slice Timing Models
(propagation delay through
REG
REG
after clock event 1.
after clock event 2.
WOSCO
,
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